BS IEC 61691-5:2004

FOREWORD
IEEE Introduction
1 Overview
   1.1 Scope
   1.2 Purpose
   1.3 Intent of this standard
   1.4 Structure and terminology of this standard
   1.5 Syntactic description
   1.6 Semantic description
   1.7 Front matter, examples, figures, notes, and annexes
2 References
3 Basic elements of the VITAL ASIC modeling specification
   3.1 VITAL modeling levels and compliance
   3.2 VITAL standard packages
   3.3 VITAL specification for timing data insertion
4 The Level 0 specification
   4.1 The VITAL_Level 0 attribute
   4.2 General usage rules
   4.3 The Level 0 entity interface
   4.4 The Level 0 architecture body
5 Backannotation
   5.1 Backannotation methods
   5.2 The VITAL SDF map
6 The Level 1 specification
   6.1 The VITAL_Level1 attribute
   6.2 The Level 1 architecture body
   6.3 The Level 1 architecture declarative part
   6.4 The Level 1 architecture statement part
7 Predefined primitives and tables
   7.1 VITAL logic primitives
   7.2 VitalResolve
   7.3 VITAL table primitives
8 Timing constraints
   8.1 Timing check procedures
   8.2 Modeling negative timing constraints
9 Delay selection
   9.1 VITAL delay types and subtypes
   9.2 Transition dependent delay selection
   9.3 Glitch handling
   9.4 Path delay procedures
   9.5 Delay selection in VITAL primitives
   9.6 VitalExtendToFillDelay
10 The Level 1 Memory specification
   10.1 The VITAL Level 1 Memory attribute
   10.2 The VITAL Level 1 Memory architecture body
   10.3 The VITAL Level 1 Memory architecture
        declarative part
   10.4 The VITAL Level 1 Memory architecture
        statement part
11 VITAL Memory function specification
   11.1 VITAL memory construction
   11.2 VITAL memory table specification
   11.3 VitalDeclareMemory
   11.4 VitalMemoryTable
   11.5 VitalMemoryCrossPorts
   11.6 VitalMemoryViolation
12 VITAL memory timing specification
   12.1 VITAL memory timing types
   12.2 Memory Output Retain timing behavior
   12.3 VITAL Memory output retain timing specification
   12.4 Transition dependent delay selection
   12.5 VITAL memory path delay procedures
   12.6 VITAL memory timing check procedures
13 The VITAL standard package
   13.1 VITAL_Timing package declaration
   13.2 VITAL_Timing package body
   13.3 VITAL_Primitives package declaration
   13.4 VITAL_Primitives package body
   13.5 VITAL_Memory package declaration
   13.6 VITAL_Memory package body
Annex A (informative) Syntax summary
Annex B (informative) Glossary
Annex C (informative) Bibliography
Annex D (informative) List of Participants

Provides method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.

Providse a standard method of modeling ASICs in VHDL.This method is aimed at providing efficient, accurate,and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs. This publication has the status of a double logo IEEE/IEC standard