BS IEC 62528:2007

IEEE Introduction
1 Overview
   1.1 Scope
   1.2 Purpose
2 Normative references
3 Definitions, acronyms, and abbreviations
   3.1 Definitions
   3.2 Acronyms and abbreviations
4 Structure of this standard
   4.1 Specifications
   4.2 Descriptions
5 Introduction and motivations of two compliance levels
6 Overview of the IEEE 1500 scalable hardware architecture
   6.1 Wrapper serial port (WSP)
   6.2 Wrapper parallel port (WPP)
   6.3 Wrapper instruction register (WIR)
   6.4 Wrapper bypass register (WBY)
   6.5 Wrapper boundary register (WBR)
7 WIR instructions
   7.1 Introduction
   7.2 Response of the wrapper circuitry to instructions
   7.3 Wrapper instruction rules and naming convention
   7.4 WS_BYPASS Instruction
   7.5 WS_EXTEST instruction
   7.6 WP_EXTEST instruction
   7.7 Wx_EXTEST instruction
   7.8 WS_SAFE instruction
   7.9 WS_PRELOAD instruction
   7.10 WP_PRELOAD instruction
   7.11 WS_CLAMP instruction
   7.12 WS_INTEST_RING instruction
   7.13 WS_INTEST_SCAN instruction
   7.14 Wx_INTEST instruction
8 Wrapper serial port (WSP)
   8.1 WSP terminals
9 Wrapper parallel port (WPP)
   9.1 WPP terminals
10 Wrapper instruction register (WIR)
   10.1 WIR configuration and DR selection
   10.2 WIR design
   10.3 WIR operation
11 Wrapper bypass register (WBY)
   11.1 WBY register configuration and selection
   11.2 WBY design
   11.3 WBY operation
12 Wrapper boundary register (WBR)
   12.1 WBR structure and operation
   12.2 WBR cell structure and operation
   12.3 WBR operation events
   12.4 WBR operation modes
   12.5 Parallel access to the WBR
   12.6 WBR cell naming
   12.7 WBR cell examples
   12.8 IEEE 1500 WBR example
13 Wrapper states
   13.1 Wrapper Disabled and Wrapper Enabled states
14 WSP timing diagram
   14.1 Specifications
   14.2 Description
   14.3 Synchronous reset timing
15 WSP configurations for IEEE 1500 system chips
   15.1 Connecting multiple WSPs
16 Plug-and-play (PnP)
   16.1 Background and definition
   16.2 PnP aspects of standard instructions
   16.3 PnP limitations on protocols
   16.4 Non-PnP in IEEE Std 1500
17 Compliance definitions common to wrapped and unwrapped cores
   17.1 General rules
   17.2 Per-terminal rules
   17.3 Test pattern information rules
18 Compliance definitions specific to unwrapped cores
   18.1 General rules
   18.2 Per-terminal rules
   18.3 Additional test information rules
19 Compliance definitions specific to wrapped cores
   19.1 General rules
   19.2 Per-terminal rules
   19.3 Wrapper protocol information rules
20 IEEE 1500 application
   20.1 CTL (IEEE P1450.6) overview
   20.2 IEEE 1500 examples
Annex A (normative) - Bubble diagram definition
Annex B (informative) - WBR cell examples
Annex C (informative) - Relationship of IEEE Std 1500 to
                        IEEE Std 1149.1
Annex D (informative) - List of participants

Defines a scalable architecture for independent, modular test development and test application for embedded design blocks and also enables test of the external logic surrounding these cores.

Defines a mechanism for the test of core designs within a system on chip (SoC).This mechanism constitutes a hardware architecture and leverages the core test language (CTL)to faciliate communication between core designers and core integrators.