BS ISO/IEC 10861:1994

1. General overview to the IEEE 1296 Standard
1.1 Scope
1.2 Normative references
2. Definitions
3. Guide to notation
3.1 General
3.2 Signal notation
3.3 Figure notation
3.4 Notation in state-flow diagrams
3.5 Notation for multiple bit data representation
4. PSB overview
4.1 General
4.2 Address/data path and system control signals
4.3 Message-passing facility
4.4 Interconnect facility
4.5 Synchronous operation of the PSB
4.6 Bus operations on the PSB
4.7 Central services module
5. Signal descriptions
5.1 General
5.2 Signal groups
6. PSB protocol
6.1 General
6.2 Arbitration operation
6.3 Transfer operation
6.4 Exception operation
6.5 Central control functions
6.6 State-flow diagrams
7. Electrical characteristics
7.1 General
7.2 AC timing specifications
7.3 DC specifications for signals
7.4 Current limitations per connector
7.5 Pin assignments
8. Mechanical specifications
8.1 General
8.2 Board sizes and dimensions
8.3 Printed board layout considerations
8.4 Front panel
8.5 Connectors
8.6 Backplanes
9. IEEE 1296 System Interface specification
9.1 Overview
9.2 Interconnect space operation
9.3 I/O space operation
9.4 Memory space operations
9.5 Message space operations
10. IEEE 1296 capabilities
10.1 Characteristic codes
Annex A. Recommended documentation practices

Defines a high-performance 32-bitsynchronous bus standard. Meant to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system. Intended for general purpose applications to optimise block transfers, including protocol for message passing.

This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard. The bus standard must have a design-in lifetime of 10 years with backward compatibility. The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time. The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1,1 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements. Options within the standard will be clearly identified. The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system. The standard is intended to support heterogeneous processor types in the same system. Message-passing format and protocol is intended for future migration to a serial system bus.