EN 60191-6-16:2007

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Mechanical standardization of semiconductor devices - Part 6-16: Glossary of semiconductor tests and burn-in sockets for BGA, LGA, FBGA and FLGA

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Published date: 20-06-2007

Publisher: European Committee for Standards - Electrical

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Table of Contents - (Show below) - (Hide below)

Foreword
1 Scope
2 Normative references
3 Terms and definitions
Annex ZA (normative) Normative references to international
publications with their corresponding European
publications

Abstract - (Show below) - (Hide below)

Gives a glossary of semiconductor sockets for BGA, LGA, FBGA and FLGA. Intends to establish definitions and unification of terminology relating to tests and burn-in sockets for BGA, LGA, FBGA and FLGA

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Committee	CLC/SR 47D
Document Type	Standard
ISBN
Pages
Published
Publisher	European Committee for Standards - Electrical
Status	Current

National Adoptions - (Show below) - (Hide below)

Equivalent Standard(s)	Relationship
BS EN 60191-6-16:2007	Identical
I.S. EN 60191-6-16:2007	Identical
PN EN 60191-6-16 : 2007	Identical
NBN EN 60191-6-16 : 2007	Identical
DIN EN 60191-6-16:2007-11	Identical
NEN EN IEC 60191-6-16 : 2007	Identical
CEI EN 60191-6-16 : 2008	Identical
IEC 60191-6-16:2007	Identical
NF EN 60191-6-16 : 2013	Identical
UNE-EN 60191-6-16:2007	Identical
BS EN 61249-4-18:2013	Identical

Standards Referencing This Book - (Show below) - (Hide below)

IEC 60191-1:2007	Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices
IEC 60191-2:2012 DB	Mechanical standardization of semiconductor devices - Part 2: Dimensions
EN 60191-3:1999	Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits
IEC 60191-4:2013	Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages
IEC 60191-3:1999	Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits

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