EN 61188-5-2:2003

1 Scope
2 Normative references
3 Packaging
4 Fixed rectangular chip resistors
   4.1 Introductory remark
   4.2 Component description
   4.3 Component dimensions
   4.4 Solder joint fillet design
   4.5 Land pattern dimensions
5 Fixed cylindrical chip resistors
   5.1 Introductory remark
   5.2 Component description
   5.3 Component dimensions
   5.4 Solder joint fillet design
   5.5 Land pattern dimensions
6 Fixed multilayer ceramic chip capacitors
   6.1 Introductory remark
   6.2 Component description
   6.3 Component dimensions
   6.4 Solder joint fillet design
   6.5 Land pattern dimensions
7 Fixed tantalum chip capacitors
   7.1 Introductory remark
   7.2 Component description
   7.3 Component dimensions
   7.4 Solder joint fillet design
   7.5 Land pattern dimensions
8 Fixed aluminium electrolytic chip capacitors with non-solid
   electrolyte (vertical type)
   8.1 Introductory remark
   8.2 Component description
   8.3 Component dimensions
   8.4 Solder joint fillet design
   8.5 Land pattern dimensions
9 Fixed aluminium electrolytic chip capacitors with non-solid
   electrolyte (horizontal type)
   9.1 Introductory remark
   9.2 Component description
   9.3 Component dimensions
   9.4 Solder joint fillet design
   9.5 Land pattern dimensions
10 Fixed film chip capacitors
   10.1 Introductory remark
   10.2 Component description
   10.3 Component dimensions
   10.4 Solder joint fillet design
   10.5 Land pattern dimensions
11 Fixed chip inductors (multilayer type)
   11.1 Introductory remark
   11.2 Component description
   11.3 Component dimensions
   11.4 Solder joint fillet design
   11.5 Land pattern dimensions
12 Fixed chip inductors (wire wound type)
13 SC-59/TO-236 - Transistors
14 SC-62/TO-243 - Transistors
15 SC-61/TO-253 - Transistors
16 SC-73 - Diodes
17 SC-63/TO-252 - Transistors
18 SC-77 - Transistors
Figures
Annex ZA (normative) Normative references to international
         publications with their corresponding European
         publications

Provides information on land pattern geometries used for the surface attachment of discrete electronic components. Provides the appropriate size, shape and tolerances of surface mount land patterns to ensure sufficient area for the appropriate solder fillet, and also allow for inspection, testing and rework of resulting solder joints.