I.S. EN 60191-3:2000
Current
The latest, up-to-date edition.
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 3 - GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF INTEGRATED CIRCUITS
Hardcopy , PDF
English
01-01-2000
For Harmonized Standards, check the EU site to confirm that the Standard is cited in the Official Journal.
Only cited Standards give presumption of conformance to New Approach Directives/Regulations.
Dates of withdrawal of national standards are available from NSAI.
1. General
2. Terminology and definitions
3. Cross-referencing of packages
4. Terminal identification - Numbering of terminals
5. Dimensions and reference letter symbols
6. Drawing layout
7. Dimensioning and tolerances
8. Inter-conversion of inch and millimetre dimensions, and
rules for rounding-off
9. Definition of families
10.Examples of drawings
11.Design procedure for dimensions of integrated circuit
packages
12.Rules for mounting integrated circuit packages into carriers
13.Bending of terminals of QUIL packages
14.Pin grid arrays
15.Rule for orientation of integrated circuit packages in
handling and shipping carriers such as stick magazines and
rails
Annex A (normative) Limits applicable for the dimensions of
integrated circuit package outlines
Annex B (informative) Example drawings showing cross-
referencing of packages, utilization of reference
letter symbols, terminal identification and index area
Annex C (normative) Terminal identification and numbering of
terminals of devices with terminals disposed in three
or more rows in each orthogonal direction
Annex D (normative) Recommended dimensions of integrated
circuit packages of form G family
Annex E (normative) General rules for the preparation of
outline drawings of packages of form G intended for
automated handling
Annex F (normative) General rules for the preparation of
outline drawings of pin grid arrays
Annex G (normative) Rule for orientation of integrated circuit
packages in handling and shipping carriers such as
stick magazines and rails
Annex H (normative) Bottom view method for terminal No.1
recognition
Annex K (normative) Gate burrs, mold flash and protrusions
Annex ZA (normative) Normative references to international
publications with their corresponding European
publications
Covers guidance on the preparation of drawings of integrated circuits outlines.
DevelopmentNote |
For CENELEC adoptions of IEC publications, please check www.iec.ch to be sure that you have any corrigenda that may apply. (01/2017)
|
DocumentType |
Standard
|
Pages |
124
|
PublisherName |
National Standards Authority of Ireland
|
Status |
Current
|
Standards | Relationship |
UNE-EN 60191-3:2001 | Identical |
SN EN 60191-3 : 1999 | Identical |
BS EN 60191-3:2000 | Identical |
NBN EN 60191-3 : 2000 | Identical |
EN 60191-3:1999 | Identical |
NF EN 60191-3 : 2000 | Identical |
IEC 60191-3:1999 | Identical |
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