IEC 62016:2003

FOREWORD
INTRODUCTION
1 Scope and object
2 Reference documents
3 General modelling issues
   3.1 Ownership and reference
   3.2 Uniqueness by value
   3.3 Default values
   3.4 Optional versus empty sets
   3.5 Model topology
4 Concepts
   4.1 The information base
   4.2 Global ports and global port bundles
   4.3 Libraries
   4.4 Cells
   4.5 Clusters and cell representation sets
   4.6 Cell representations
   4.7 Master ports and master port bundles
   4.8 Instances
   4.9 Instance ports and instance port bundles
5 Connectivity
   5.1 Logical connectivity
   5.2 Structural connectivity with wide instances
   5.3 Structural connectivity of connectivity views
6 The design hierarchy mechanism
   6.1 The design hierarchy
   6.2 Annotations
7 Core Model for electronic design
   7.1 Libraries
   7.2 Interfacing to cells
   7.3 Cell definition hierarchies
   7.4 Instantiation
   7.5 Logical connectivity
   7.6 Structural connectivity
   7.7 Global connectivity
   7.8 Design and configuration
   7.9 Annotation
8 Core Model EXPRESS-G
   8.1 Partial EXPRESS-G of cell
   8.2 Partial EXPRESS-G of cell_representation
   8.3 Partial EXPRESS-G of cluster
   8.4 Partial EXPRESS-G of cluster_configuration
   8.5 Partial EXPRESS-G of cluster_interface
   8.6 Partial EXPRESS-G of connectivity_generic_bus
   8.7 Partial EXPRESS-G of connectivity_generic_net
   8.8 Partial EXPRESS-G of design
   8.9 Partial EXPRESS-G of global_port
   8.10 Partial EXPRESS-G of information_base
   8.11 Partial EXPRESS-G of instance
   8.12 Partial EXPRESS-G of instance_configuration
   8.13 Partial EXPRESS-G of library
   8.14 Partial EXPRESS-G of master_port_annotate
   8.15 Partial EXPRESS-G of name_information
   8.16 Partial EXPRESS-G of occurrence_annotate
   8.17 Partial EXPRESS-G of occurrence_annotate
   8.18 Partial EXPRESS-G of occurrence_annotate
   8.19 Partial EXPRESS-G of occurrence_hierarchy_annotate
   8.20 Partial EXPRESS-G of port_structure
   8.21 Partial EXPRESS-G of property
   8.22 Partial EXPRESS-G of property_override
   8.23 Partial EXPRESS-G of signal
9 Core Model schemas
   9.1 connectivity_structure_model
   9.2 connectivity_view_model
   9.3 design_hierarchy_model
   9.4 design_management_model
   9.5 documentation_model
   9.6 hierarchy_model
   9.7 information_base_model
   9.8 library_model
   9.9 logical_connectivity_model
   9.10 support_definition_model
10 Core Model information model
   10.1 connectivity_structure_model
   10.2 design_hierarchy_model
   10.3 documentation_model
   10.4 hierarchy_model
   10.5 information_base_model
   10.6 support_definition_model
11 Index
Figures

Provides the semantics definitions for the categories of information related to electronic circuit designs. Each category of design information is modelled as an EXPRESS schema