IEC PAS 62123:1999

1 Scope
2 Referenced Documents
      2.1 Japan Printed Circuits Association 1
      2.2 International Electrotechnical Commission
      2.3 IPC
3 Definitions of Terms
4 Test Methods
5 Performance Levels
6 Base Materials
7 Visual Inspection
      7.1 Test Environment
      7.2 Test Specimens
      7.3 Tools for Testing
      7.4 Preparation of Limit Samples
      7.5 Description of Inspections
             7.5.1 Visual Inspection of Conductors
             7.5.2 Visual Inspection of Base Film
             7.5.3 Visual Inspection of Coverlay and
                      Covercoat
             7.5.4 Visual Inspection of Plating
             7.5.5 Visual Inspection of Edges of Outline
                      and Holes
             7.5.6 Visual Imperfections Related to
                      Stiffener Bonding
             7.5.7 Other Visual Inspection
8 Dimensional Inspections
      8.1 Measurement of Dimensions
      8.2 External Dimensions
      8.3 Thickness
      8.4 Holes
             8.4.1 Component Holes
             8.4.2 Vias
             8.4.3 Mounting Holes
      8.5 Conductor Widths
      8.6 Clearances between Conductors
      8.7 Distance between Hole Centers
      8.8 Minimum Distance between Board Edges and
             Conductors
      8.9 Positional Accuracy
             8.9.1 Positional Accuracy of Holes
             8.9.2 Registration of Hole to Land
             8.9.3 Registration of Coverlay (or Covercoat)
                      to Land
             8.9.4 Registration to Stiffener to FPC
             8.9.5 Registration of Punched Outline to
                      Conductor Patterns
      8.10 Registration of Pressure Sensitive or Heat
             Activated Adhesives (including Adhesive
             Squeeze-Out) to Flexible Printed Board and
             Stiffener
      8.11 Plating Thickness of Copper Plated-Through Holes
9 Testing of Electrical Performance
10 Testing of Mechanical Performance
11 Environmental Performance
12 Migration
13 Chemical Resistance
14 Cleanliness
15 Flame Resistance
16 Marking, Packaging, and Storage
      16.1 Marking on Products
      16.2 Marking on Package
      16.3 Packaging and Storage
             16.3.1 Packaging
             16.3.2 Storage
             16.3.3 Handling
Appendix I
Appendix II
Appendix III
Figure 1 - Nicks and Pinholes in Conductor
Figure 2 - Reduced Area on Land
Figure 3 - Circumferential Void at the Component Hole Corner
Figure 4 - Extraneous Copper between Conductors/Spurs and
           Nodules of Conductors Corner
Figure 5 - Extraneous Copper and Spurs and Nodules in Open
           Area and Nodules of Conductors Corner
Figure 6 - Etched Concave on Conductor Surface and Nodules of
           Conductors Corner
Figure 7 - Conductor Delamination
Figure 8 - Scratches on Conductor
Figure 9 - Dents
Figure 10 - Scratch on Base Film
Figure 11 - Allowable Voids
Figure 12 - Foreign Matters
Figure 13 - Lifting and Delamination of Coverlay and Covercoat
Figure 14 - Allowable Squeeze-Out of Coverlay - Adhesive and
            Ooze-Out of Covercoat
Figure 15 - Plating Defects
Figure 16 - Penetration of Plated Metal or Solder
Figure 17 - Plating Voids in Plated-Through Hole
Figure 18 - Tears and Nicks
Figure 19 - Burrs
Figure 20 - Thready Burrs
Figure 21 - Foreign Matter between Board and Stiffener
Figure 22 - Voids between Board and Stiffener
Figure 23 - Cracks
Figure 24 - Chip-Off
Figure 25 - Protrusions and Dents on Flexible Printed Board
Figure 26 - Bow and Twist
Figure 27 - Misregistration of Hole and Land
Figure 28 - Misregistration of Land and Coverlay (or
            Covercoat)
Figure 29 - Registration of Holes
Figure 30 - Registration of Outlines
Figure 31 - Registration of Pressure Sensitive or Heat
            Activated Adhesives from Flexible Printed Board
            and Stiffener (including Adhesive Squeeze-Out)
Table 1 - Allowable Nicks and Pinholes
Table 2 - Allowable Extraneous Copper and Spurs and Nodules
          between Conductors
Table 3 - Allowable Etched Concave on Conductor Surface
Table 4 - Allowable Conductor Delamination
Table 5 - Allowable Scratches on Conductor
Table 6 - Allowable Dents
Table 7 - Discoloration
Table 8 - Dents
Table 9 - Allowable Scratches on Base Film
Table 10 - Dents on Coverlay and Covercoat
Table 11 - Requirements for Scratches on Coverlay and
           Covercoat
Table 12 - Allowable Voids
Table 13 - Allowable Non-Conductive Foreign Materials (mm)
Table 14 - Allowable Squeeze-Out of Coverlay Adhesive and
           Ooze-Out of Covercoat
Table 15 - Minimum Solderable Annular Ring on Land Area
Table 16 - Gold Plating
Table 17 - Requirements for Metal Penetration between
           Conductor and Coverlay
Table 18 - Requirements for Metal Penetration between
           Conductor and Base Film
Table 19 - Gold Plating
Table 20 - Allowable Plating Voids
Table 21 - Cracks
Table 22 - Thermosetting Adhesives on Surface
Table 23 - Flux Residue on Surface
Table 24 - Residue of Metal Powders (Solder, Aluminium,
           Copper, etc.)
Table 25 - Residue of Adhesive
Table 26 - Tolerance of External Dimension
Table 27 - Requirements for Holes
Table 28 - Requirements for Vias
Table 29 - Conductor Widths and Tolerances (mm)
Table 30 - Conductor Clearances and Tolerances (mm)
Table 31 - Tolerance of Distance between Hole Centers
Table 32 - Minimum Distance between Board Edges and
           Conductors
Table 33 - Allowable Misregistration of Outlines
Table 34 - Registration of Punched Outline to Conductor
           Patterns
Table 35 - Electrical Properties of Flexible Printed Boards
Table 36 - Mechanical Properties of Flexible Printed Boards
Table 37 - Environmental Tests and Requirements
Table 38 - Requirements for Packaging