IEEE DRAFT 1149.4 : D25 FEB 99

1 Overview
1.1 Organization of the standard
1.2 Context
1.3 Scope of the standard
1.4 Background reading
2 References
3 Definitions, acronyms, and voltage symbols
3.1 Definitions
3.2 Acronyms
3.3 Voltage source symbols
4 Testability Architecture
4.1 Overview
4.2 TAP controller
4.3 Analog test access port (ATAP)
4.4 Register architecture
5 Instructions
5.1 General
5.2 Response of test logic to instructions
5.3 Mandatory instructions
5.4 Optional instructions
6 The Test Bus Interface Circuit (TBIC)
6.1 General
6.2 Test bus and TBIC structure
6.3 Control of the TBIC
6.4 Differential I/O
6.5 Partitioned internal test bus structure
7 The Boundary-Scan Register
7.1 Structure
7.2 Digital boundary modules (DBMs)
7.3 Analog boundary modules (ABMs)
7.4 Differential analog boundary modules
8 Measurement Methodology
8.1 Interconnect testing
8.2 Extended interconnect testing
8.3 Network measurements
9 Analog parametric limits
9.1 General
9.2 Switch limitations
9.3 Electrostatic protection
9.4 Performance specifications
9.5 Measuring performance
9.6 Calibration and errors
10 Conformance and Documentation
10.1 Conformance
10.2 General documentation
10.3 Documentation of residual elements

Standard defines test features to be included in mixed-signal (analog and digital) component, together with associated test protocols, to provide standardized approaches to: Interconnect Test - testing for opens and shorts among the interconnections in a PCA; Parametric Test - making analog characterization measurements - Internal Test, testing the internal circuitry of the mixed-signal component itself whether or not it is part of a PCA.