BS IEC 62525:2007

IEEE Introduction
1 Overview
   1.1 Scope
   1.2 Purpose
2 References
3 Definitions, acronyms, and abbreviations
   3.1 Definitions
   3.2 Acronyms and abbreviations
4 Structure of this standard
5 STIL orientation and capabilities tutorial (informative)
   5.1 Hello Tester
   5.2 Basic LS245
   5.3 STIL timing expressions/"Spec" information
   5.4 Structural test (scan)
   5.5 Advanced scan
   5.6 IEEE Std 1149.1-1990 scan
   5.7 Multiple data elements per test cycle
   5.8 Pattern reuse/direct access test
   5.9 Event data/non-cyclized STIL information
6 STIL syntax description
   6.1 Case sensitivity
   6.2 Whitespace
   6.3 Reserved words
   6.4 Reserved characters
   6.5 Comments
   6.6 Token length
   6.7 Character strings
   6.8 User-defined name characteristics
   6.9 Domain names
   6.10 Signal and group name characteristics
   6.11 Timing name constructs
   6.12 Number characteristics
   6.13 Timing expressions and units (time_expr)
   6.14 Signal expressions (sigref_expr)
   6.15 WaveformChar characteristics
   6.16 STIL name spaces and name resolution
7 Statement structure and organization of STIL information
   7.1 Top-level statements and required ordering
   7.2 Optional top-level statements
   7.3 STIL files
8 STIL statement
   8.1 STIL syntax
   8.2 STIL example
9 Header block
   9.1 Header block syntax
   9.2 Header example
10 Include statement
   10.1 Include statement syntax
   10.2 Include example
   10.3 File path resolution with absolute path notation
   10.4 File path resolution with relative path notation
11 UserKeywords statement
   11.1 UserKeywords statement syntax
   11.2 UserKeywords example
12 UserFunctions statement
   12.1 UserFunctions statement syntax
   12.2 UserFunctions example
13 Ann statement
   13.1 Annotations statement syntax
   13.2 Annotations example
14 Signals block
   14.1 Signals block syntax
   14.2 Signals block example
15 SignalGroups block
   15.1 SignalGroups block syntax
   15.2 SignalGroups block example
   15.3 Default attribute values
   15.4 Translation of based data into WaveformChar
         characters
16 PatternExec block
   16.1 PatternExec block syntax
   16.2 PatternExec block example
17 PatternBurst block
   17.1 PatternBurst block syntax
   17.2 PatternBurst block example
18 Timing block and WaveformTable block
   18.1 Timing and WaveformTable syntax
   18.2 Waveform event definitions
   18.3 Timing and WaveformTable example
   18.4 Rules for timed event ordering and waveform creation
   18.5 Rules for waveform inheritance
19 Spec and Selector blocks
   19.1 Spec and Selector block syntax
   19.2 Spec and Selector block example
20 ScanStructures block
   20.1 ScanStructures block syntax
   20.2 ScanStructures block example
21 STIL Pattern data
   21.1 Cyclized data
   21.2 Multiple-bit cyclized data
   21.3 Non-cyclized data
   21.4 Scan data
   21.5 Pattern labels
22 STIL Pattern statements
   22.1 Vector (V) statement
   22.2 WaveformTable (W) statement
   22.3 Condition (C) statement
   22.4 Call statement
   22.5 Macro statement
   22.6 Loop statement
   22.7 MatchLoop statement
   22.8 Goto statement
   22.9 BreakPoint statements
   22.10 IDDQTestPoint statement
   22.11 Stop statement
   22.12 ScanChain statement
23 Pattern block
   23.1 Pattern block syntax
   23.2 Pattern initialization
   23.3 Pattern examples
24 Procedures and MacroDefs blocks
   24.1 Procedures block
   24.2 Procedures example
   24.3 MacroDefs block
   24.4 Scan testing
   24.5 Procedure and Macro Data substitution
Annex A (informative) - Glossary
Annex B (informative) - STIL data model
Annex C (informative) - GNU GZIP reference
Annex D (informative) - Binary STIL data format
Annex E (informative) - LS245 design description
Annex F (informative) - STIL FAQs and language design decisions
Annex G (informative) - List of participants

Defines a test description language that: a) Facilitates the transfer of large volumes of digital test vector data from CAE environments to automated test equipment (ATE) environments; b) Specifies pattern, format, and timing information sufficient to define the application of digital test vectors to a device under test (DUT).

Defines a test description language that: Facilitates the transfer of large volumes of digital test vector data from CAE environments to automated test equipment ATE environments; Specifies pattern, format, and timing information sufficient to define the application of digital test vectors to a device under test (DUT); Supports the volume of test vector data generated from structured tests such as scan/automatic test pattern generation (ATPG), integral test techniques such as built-in self test (BIST), and functional test specifications for IC designs and their assemblies, in a format optimized for application in ATE environments.