IEEE DRAFT 1481 : D1 98

1. Overview
2. References
3. Definitions
4. Acronyms and abbreviations
5. Delays and power calculation system architecture
       5.1 Overview
       5.2 Procedural interface
       5.3 DPCM - application relationships
       5.4 Inter-operability
6. Delay Calculation Language (DCL)
       6.1 Character set
       6.2 Lexical elements
       6.3 Name spaces of identifiers
       6.4 Storage durations of objects
       6.5 Scope of identifiers
       6.6 Linkages of identifiers
       6.7 DCL data types
       6.8 Type conversions
       6.9 Operators
       6.10 Expressions
       6.11 Computation order
       6.12 DCL statements
       6.13 Tables
       6.14 Library control statements
       6.15 Modeling
       6.16 Embedded C code
       6.17 Definition of a subrule
7. Power modeling and calculation
       7.1 Power overview
       7.2 Caching state information
       7.3 Caching load and slew information
       7.4 Simultaneous switching events
       7.5 Partial swing events
       7.6 Power calculation
       7.7 Accumulation of power consumption by the design
       7.8 Group pin list syntax and semantics
       7.9 Group condition list syntax and semantics
       7.10 Sensitivity list syntax and semantics
       7.11 Group condition language
8. Procedural Interface (PI)
       8.1 Overview
       8.2 Control and data flow
       8.3 Architectural requirements
       8.4 Data ownership technique
       8.5 Application/DPCM interaction
       8.6 Re-entry requirements
       8.7 Application responsibilities when using a DPCM
       8.8 Application use of the DPCM
       8.9 DPCM library organization
       8.10 Error handling
       8.11 C level language for EXPOSE and EXTERNAL functions
       8.12 PIN data structure requirements
       8.13 DCM_STD_STRUCT Standard Structure
       8.14 DCMTransmittedInfo structure
       8.15 Environment or user variables
       8.16 PI functions summary
       8.17 PI function descriptions
       8.18 Standard structure (std_stru.h) file
       8.19 Standard macros (st_macs.h) file
       8.20 Standard interface structures (dcmintf.h) file
       8.21 Standard loading (dcmload.h) file
       8.22 Standard debug (dcmdebug.h) file
       8.23 Standard array (dcmgarray.h) file
       8.24 DCM use array defines (dcmuarray.h) file
       8.25 Standard platform-dependency (dcmpltfm.h) file
       8.26 Standard state variables (dcmstate.h) file
       8.27 Standard table descriptor (dcmutab.h)
9. Parasitics
       9.1 Introduction
       9.2 Targeted applications for SPEF
       9.3 SPEF specification
       9.4 Examples
10. Physical design exchange
       10.1 Introduction
       10.2 PDEF specification
       10.3 Examples
A. Implementation requirements
B. Calculation of total load capacitance in the DPCS
C. Hold Control
D. Bibliography
List of Figures
5-1 High-level DPCS architecture
5-2 High-level DPCS architecture linkage structure
8-1 DPCM/application procedural interface
8-2 PIN and PINLIST
8-3 PI function table example
8-4 Parallel drivers example
8-5 Capacitance value example
8-6 Passed and receiver pin pointers examples
8-7 Integer LSB example
8-8 Bias calculation
8-9 Clock separation
8-10 Different edges
8-11 Sample MODELPROC results
8-12 Additional MODELPROC results
9-1 SPEF targeted applications
10-1 PDEF targeted applications
10-2 Hierarchical routes
10-3 Clusters cross logic hierarchy
10-4 Illustrations of the chip used in the example
10-5 A global route
10-6 Symbolic cell and cluster placement
10-7 Symbolic pin and net placement
C.1 Transparent latch pair feedback
C.2 Overlap period
C.3 Padding the paths
C.4 Stable overlap period
C.5 Hold Control modeling
C.6 Snipped feedback line
List of Tables
6-1 Keywords
6-2 DCL predefined references to Standard Structure fields
6-3 DCL compiler generated predefined identifiers
6-4 Edge types and conversions
6-5 Propagation mode conversions
6-6 Calculation mode conversions
6-7 TEST_TYPE conversions
6-8 VAR array modifier
6-9 Purity operator
6-10 Timing mode semantics
6-11 Mathematical operators
6-12 Logical operators
6-13 Mathematical operator precedence (high to low)
6-14 Logical operator precedence (high to low)
6-15 Validity of predefined identifiers for STORE clause
7-1 PinName_Identifier semantics
7-2 PinName_Level semantics
7-3 PinName_State semantics
7-4 Condition expression operators
8-1 Interaction between multiple technologies and application
8-2 Return code high-order byte
8-3 Return code low-order bytes
8-4 Data types
8-5 Header files
8-6 Predefined variable names
8-7 Alternate semantics for Standard Structure fields
8-8 EXPOSE functions
8-9 EXTERNAL functions
8-10 libdcmir functions
8-11 Initialization functions
8-12 Calculation functions
8-13 Modeling functions
8-14 Standard Structure field semantics
8-15 Mask encoding
8-16 Mode operator enumerators
8-17 Mode operator enumerators for delay and slew
8-18 Mode operator enumerators for check
8-19 Enumeration pairs
8-20 Edge propagation communication with DPCM
9-1 Design flow values
9-2 conn_attr types
10-1 Netlist type identifiers
10-2 Design flow identifiers
10-3 Gate type attributes
10-4 Gate restriction attributes
10-5 Pin and gate_pin attributes
10-6 Node type attributes
10-7 Net type attributes
10-8 Net restriction attributes
10-9 Route restriction attributes
10-10 Route connectivity attributes
10-11 Cluster restriction attributes
10-12 Cluster connectivity attributes
10-13 Cell type attributes
10-14 Cell restriction attributes
10-15 Spare cell restriction attributes
10-16 Pbus and nbus type attributes
10-17 Pnet type attributes
10-18 Pnet restriction attribute pre-defined values
10-19 Gap and skip type attributes

This document is aimed towards modeling integrated circuit cell delays and power at a level of accuracy sufficient for sign-off and a level of power sufficient to support design synthesis tools.