SN EN 61943 : 1999

1 General<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;1.1 Scope and Object<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;1.2 Normative Reference<br>2 Definitions<br>3 Principles for Qualified Manufacturer List (QML) <br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Approval<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;3.1 Identification and definition of tasks<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;3.2 Product specifications<br>4 Process design (Task 1)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;4.1 Field of application<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;4.2 Description of activities<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;4.3 Interfaces and subcontracting procedures<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;4.4 Procedures for design and verification of<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;models<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;4.5 Procedures for integration and validation<br>5 Integrated Circuit Design (Task 2)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;5.1 Field of application<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;5.2 Description of activities<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;5.3 Interfaces<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;5.4 Procedures for design and verification<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;5.5 Validation procedure<br>6 Wafer Fabrication (Task 3)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;6.1 Field of application<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;6.2 Description of activities<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;6.3 Interfaces<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;6.4 Validation procedureer or subcontractor<br>7 Process Characterization (Task 4)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;7.1 Field of application<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;7.2 Description of activities<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;7.3 Characterization procedures<br>8 Assembly and Packaging (Task 5)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;8.1 Field of application<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;8.2 Description of activities<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;8.3 Interfaces<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;8.4 Validation procedures<br>9 Tests (Task 6)<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;9.1 Field of application<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;9.2 Description of activities<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;9.3 Interfaces - Validation of information provided<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;by the customer or subcontractor<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;9.4 Procedures<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;9.5 Validation procedures<br>Annex ZA (normative) Normative references to international <br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;publications with their corresponding <br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;European publications

Specifies means of applying requirements and principles provided in IEC 61739 to monolithic integrated circuits. Covers integrated circuit manufacturers who request manufacturing line approval. The aim is to establish consistency in the criteria employed by auditors and manufacturers for techniques relating to manufacture of integrated circuits. Manufacturers may employ their own procedure for meeting the requirements, given that the necessary control level in the manufacturing line is achieved.