MIL-STD-2000 Revision A:1991

1. SCOPE
1.1 Scope
1.2 Discrete device exclusion
1.3 Other applications
2. APPLICABLE DOCUMENTS
2.1 Government documents
2.2 Non-Government publications
2.3 Order of precedence
3. TERMS AND DEFINITIONS
3.1 Terms and definitions
4. GENERAL REQUIREMENTS
4.1 Interrelation of applicable documents
4.2 Visual aids
4.3 Workmanship
4.4 Disposition of defects
4.5 Harness and cable assemblies
4.6 Materials
4.7 Printed wiring
4.8 Solder mask
4.9 Conformal coating of all assemblies
4.10 Interference spacing
4.11 Eyelets
4.12 Detailed part mounting
4.13 Component misregistration
4.14 Coefficient of Thermal Expansion (CTE) mismatch
        compensation
4.15 Lead bends
4.16 Stress relief
4.17 Devices mounted over circuitry
4.18 Stacking (piggybacking)
4.19 Adhesive coverage limits
4.20 General solder connection characteristics
4.21 General printed wiring requirements
4.22 Through-hole solder connections
4.23 Surface mount solder connections
4.24 Attachment of leads and wires
4.25 Terminal and connector configuration
4.26 Part markings and reference designations
5. DETAIL REQUIREMENTS
5.1 Latent failure prevention
5.2 Defect prevention
5.3 Process controls and defect reduction
6. NOTES
6.1 Manufacture of devices incorporating magnetic
        windings
6.2 Guidance on requirement flowdown
6.3 Guidance on inspection power selection and
        defect identification
6.4 Supersession note
6.5 Subject term (key word) listing
6.6 Use of metric units
6.7 Changes from previous issue
Figures
1. Flat bodied terminal
2. Lead bends
3. Typical stress relief bends
4. Plated-through hole interfacial and interlayer
      connections
5. Solder in the lead bend radius
6. Chip resistor
7. Mounting of chips
8. Chip side overhang
9. Minimum lap of chip on terminal area
10. Solder fillet - chip devices
11. Excessive solder - parts encased
12. Mounting of MELFs
13. MELF solder fillet
14. Leadless chip carrier solder fillet
15. Parallelism of chip devices
16. Surface mounted device lead forming
17. Lead overhang
18. Surface mounted device lead toe overhang
19. Surface mounted device lead heel clearance
20. Surface mounted device lead height off land
21. Surface mounted device round or coined lead
      solder fillet
22. J-lead and V-lead solder fillet
23. Maximum chip canting
24. Wire and lead wrap/continuous runs
25. Wire and lead soldering to small slotted terminal
26. Wire and lead soldering to contacts
27. Wire and lead soldering to solder cups
28. Internal connector lead configurations
Tables
I. Defects
II. Conductor spacing (uncoated printed wiring boards)
      (sea level to 10,000 feet)
III. Conductor spacing (uncoated printed wiring boards)
      (over 10,000 feet)
IV. Contamination limits
Appendix A
10. Scope
20. Applicable documents
30. Terms and definitions
40. General requirements
Appendix B
10. Scope
20. Applicable documents
30. Terms and definitions
40. General requirements
Figures
B-1. Lead termination (clinched leads)
B-2. Blocked plated-through holes
B-3. Clinched wire interfacial connections
B-4. Meniscus clearance
B-5. Mounting of freestanding nonaxial-leaded
      components
B-6. Typical standoff devices (footed)
B-7. Mounting components using standoffs
B-8. Typical standoff devices (internal cavities)
B-9. Rolled flange terminals
B-10. Flare and extension of funnel flanges
B-11. Dual hole configuration for interfacial and inter-
      layer terminal mountings
B-12. Standoff terminal interfacial connection
B-13. Stress relief for lead wiring
B-15. Lead dress
B-16. Side route connections and wrap on bifurcated
      terminals
B-17. Typical pierced or perforated terminal wire wrap
B-18. Body positioning of part with coined lead
Appendix C
10. Scope
20. Applicable documents
30. Terms and definitions
40. General requirements
Tables
C-I. Cleanliness test values
C-II. Equivalence factors for testing ionic contamination

Specifies materials and methods for creating soldered electrical and electronic connections. Coverage includes applicable documents, interrelation of applicable documents, specialised technologies, disposition of defects, process variances, materials, solder, flux, use of nonrosin fluxes, workmanship, visual aids, conductor finish, partial hole fill, stacking of chips, and wire and strand condition. Also gives terms and definitions.