DD IEC/TS 62215-2:2007

INTRODUCTION
1 Scope
2 Normative references
3 Terms and definitions
4 General
  4.1 Introduction
  4.2 Measurement philosophy
  4.3 Set-up concept
  4.4 Response signal
  4.5 Coupling networks
      4.5.1 General
      4.5.2 Design of coupling networks
      4.5.3 Coupling network for the ground/V[ss] pin(s)
      4.5.4 Coupling network for the supply/V[dd] pin(s)
      4.5.5 Coupling network for the I/O pin(s)
      4.5.6 Coupling network for the reference pins
      4.5.7 Coupling network verification
  4.6 Test circuit board
      4.6.1 General
      4.6.2 IC pin loading/termination
      4.6.3 Power supply requirements
  4.7 IC specific considerations
      4.7.1 IC supply voltage
      4.7.2 IC decoupling
      4.7.3 Activity of IC
      4.7.4 Guidelines for IC stimulation
      4.7.5 IC monitoring
      4.7.6 IC stability over time
5 Test conditions
  5.1 Default test conditions
      5.1.1 General
      5.1.2 Ambient conditions
      5.1.3 Ambient temperature
  5.2 Impulse immunity of the test set-up
6 Test set-up
  6.1 General
  6.2 Test equipment
  6.3 Set-up explanation
  6.4 Explanation of signal relations
  6.5 Calculation of time step and number of measurements
      to be conducted
  6.6 Test procedure
  6.7 Monitoring check
  6.8 System verification
7 Test report
  7.1 General
  7.2 Immunity limits or levels
  7.3 Performance classes
  7.4 Interpretation and comparison of results
Annex A (informative) - Flow chart of the software used in
        a microcontroller
Annex B (informative) - Flow chart for the set-up control
        S/W (bus control program)
Annex C (informative) - Test board requirements
Bibliography

Contains general information and definitions on the test method to evaluate the immunity of integrated circuits (ICs) against fast conducted synchronous transient disturbances.

Contains general information and definitions on the test method to evaluate the immunity of integrated circuits (ICs) against fast conducted synchronous transient disturbances.The objective is to describe general conditions to obtain a quantitative measure of immunity of ICs establishing a uniform testing environment. Critical parameters that are expected to influence the test results are described. Deviations from this specification should be explicitly noted in the individual test report. This synchronous transient immunity measurement method uses short impulses with fast rise times of different amplitude, duration and polarity in a conductive mode to the IC. In this method, the applied impulse has to be synchronized with the activity of the IC to make sure that controlled and reproducible conditions can be assured