IEC PAS 62085:1998

1 SCOPE
    1.1 Purpose
    1.2 Categorization
    1.3 Presentation
    1.4 Producibility Levels
2 TECHNOLOGY OVERVIEW OF BOARD AND ASSEMBLY REQUIREMENTS
    2.1 The Drivers for Component Packaging
          2.1.1 The Thermal Drivers
          2.1.2 The Electric Drivers
          2.1.3 The Real Estate Drivers
          2.1.4 Specific Package Drivers
    2.2 Issues in Component Packaging
          2.2.1 Future Considerations
    2.3 Impact on Interconnecting (Printed Board)
          Technology
    2.4 Impact on Assembly
    2.5 Future Implementation Strategies
          2.5.1 Complexity Matrix
3 COMPONENT PACKAGES
    3.1 Component Identification
          3.1.1 Area Array Component Types
          3.1.2 Peripheral Leaded Devices Packages
          3.1.3 Component Marking
    3.2 Component Materials
          3.2.1 Ball/Column Termination
          3.2.2 Termination Leads
          3.2.3 Plating and Coating Technologies
          3.2.4 Process Comparisons
          3.2.5 Plastic Packages
          3.2.6 Ceramic Packages
          3.2.7 Die Attach
    3.3 Heat Dissipation Techniques
          3.3.1 Conduction
          3.3.2 Convection
          3.3.3 Radiation
          3.3.4 Thermal Impedance
          3.3.5 Component Level Thermal Characteristics
          3.3.6 Board Level Thermal Management
    3.4 Handling and Storage
          3.4.1 ESD
4 PACKAGE DETAILS
    4.1 Area Array Package Description
          4.1.1 Physical Properties
          4.1.2 Bump/Termination Layout
          4.1.3 Standardization
    4.2 BGA Types
          4.2.1 Plastic BGA
          4.2.2 Thermally Enhanced BGA
          4.2.3 Tab BGA
          4.2.4 Mini BGA
          4.2.5 Micro BGA
          4.2.6 Ceramic Ball Grid Array (CBGA)
    4.3 Material Decisions
          4.3.1 Thin Film Redistribution
          4.3.2 Coplanarity
          4.3.3 "Popcorning Effect" Failure
    4.4 Area Array Selection Process
          4.4.1 Device Outlines
          4.4.2 Array Population
    4.5 Peripheral Lead Package Descriptions
          4.5.1 Lead Pitch Parameters
          4.5.2 Standard SMT
          4.5.3 Fine Pitch Packages
          4.5.4 Ultra Fine Pitch Packages
    4.6 Sockets
          4.6.1 ZIF Sockets
          4.6.2 LIF Sockets
5 INTERCONNECTING STRUCTURES
    5.1 Interconnecting Structure Descriptions
          5.1.1 Rigid Printed Boards
          5.1.2 Flexible Printed Wiring Boards
          5.1.3 Encapsulated Discrete Wire Interconnection
                  Boards
          5.1.4 Nonorganic (Ceramic) Structures
    5.2 Material Selection
          5.2.1 Reinforcement Material Properties
          5.2.2 Resin Types
          5.2.3 Permanent Polymers (Solder Resist)
          5.2.4 Metallic Foils and Films
    5.3 Manufacturing Options
          5.3.1 Physical Parameters
          5.3.2 Image Transfer
          5.3.3 Feature Characteristics (Size, Shape,
                  Tolerances)
    5.4 Conductor Routing Methodologies
          5.4.1 Wiring Via Densities
          5.4.2 Conductors Geometries
          5.4.3 Signal Routing
          5.4.4 Fine Line/Circuit Layer Trade-offs
    5.5 Test Methodology
          5.5.1 Electrical Continuity
          5.5.2 Electrical High Frequency
          5.5.3 High Acceleration Stress Test
6 ASSEMBLY PROCESSES
    6.1 Assembly Classification
          6.1.1 Process Flow, Type 1
          6.1.2 Process Flow, Type 2
    6.2 Assembly Materials
          6.2.1 Surface Mount Adhesives
          6.2.2 Conductive Adhesives
          6.2.3 Soldering Fluxes
          6.2.4 Solder Alloys
          6.2.5 Solder Paste
    6.3 Equipment Characteristics
          6.3.1 Adhesive and Solder Paste Application
          6.3.2 Placement
          6.3.3 Fiducial Targets
          6.3.4 Soldering
          6.3.5 Cleaning (General)
          6.3.6 Rework
    6.4 Package Attachment Process Details
          6.4.1 Substrate Preparation
          6.4.2 Component Preparation
          6.4.3 Heat Sink Attachment
          6.4.4 Process Control
          6.4.5 Process Comparison
    6.5 Assembled Board Test
          6.5.1 Test Strategy
          6.5.2 In-Circuit ATE Access
          6.5.3 Locating Open Solder Joints at ATE
          6.5.4 Functional Test
          6.5.5 Manual Access for Debug (at ATE or
                  Functional Test)
7 DESIGN FOR RELIABILITY (DfR)
    7.1 Damage Mechanisms and Failure of Solder Attachments
          7.1.1 Solder Joints and Attachment Types
          7.1.2 Global Expansion Mismatch
          7.1.3 Local Expansion Mismatch
          7.1.4 Internal Expansion Mismatch
          7.1.5 Solder Attachment Failure
    7.2 Reliability Prediction Modeling
          7.2.1 Creep-Fatigue Modeling
          7.2.2 Statistical Failure Distribution and
                  Failure Probability
          7.2.3 Damage Modeling
          7.2.4 Caveat 1 - Solder Joint Quality
          7.2.5 Caveat 2 - Large Temperature Excursions
          7.2.6 Caveat 3 - High Frequency/Low-Temperatures
          7.2.7 CAVEAT 4 - Local Expansion Mismatch
          7.2.8 Caveat 5 - Very Stiff Leads
          7.2.9 Caveat 6 - Very Soft Leads/Very Large
                  Expansion Mismatches
          7.2.10 Multiple Cyclic Load Histories
          7.2.11 System Reliability Evaluation
    7.3 DfR-Process
    7.4 Validation and Qualification Tests
    7.5 Screening Procedures
          7.5.1 Solder Joint Defects
          7.5.2 Screening Recommendation
    7.6 Reliability Expectations
          7.6.1 Life Expectancy
          7.6.2 Use Environments
          7.6.3 Electrical Testing/Performance
          7.6.4 Burn In
          7.6.5 Product Performance Simulation
8 STANDARDIZATION
    8.1 Standards for Development
    8.2 Ball Grid Array Development and Performance
          Standards
          8.2.1 Ball Grid Array Component Design
          8.2.2 Performance Requirements for Solder Bumps
    8.3 Standard on Mounting of Substrate Design and
          Performance
          8.3.1 Design Standard for Ball Grid Array Package
                  Mounting
          8.3.2 Qualification and Performance of Organic
                  Mounting Structures intended for BGA
                  Mounting
          8.3.3 Qualification and Performance of Inorganic
                  Mounting Structures Intended for BGA
                  Mounting
          8.3.4 Qualification, Quality Conformance, and
                  In-process Test Methods used for Organic/
                  Inorganic Flip Chip Mounting Structures
    8.4 Ball Grid Array/Substrate Assembly Design and
          Performance Standards
          8.4.1 Ball Grid Array Assembly Design
          8.4.2 Assembly Performance Requirements
          8.4.3 Assembly Test Methods
          8.4.4 Qualification and Performance of Rework
                  and Repair of BGA Assembly
    8.5 Standards for Material Performance
         8.5.1 Flux for BGA Mounting Applications
9 FUTURE NEEDS
    9.1 Critical Factor: Manufacturing Infrastructure
          9.1.1 Materials
          9.1.2 Equipment
          9.1.3 Design
    9.2 Critical Factor: Bump Attachment and Bonding
          9.2.1 Dimensional Control
          9.2.2 Metallurgical Integrity
          9.2.3 Cleanliness of Bumping Site
    9.3 Critical Factor: Testing Scenarios
          9.3.1 Critical Environmental Testing
          9.3.3 Inspection and Process Control Assurance
    9.4 Total Quality Management and Manufacturing (TQMM)
Figures 1-1 / 8-11
Tables 1-1 / 7-3

Establishes the requirements and interactions necessary for Printed Board Assembly processes for interconnecting high performance/high pin count I/C packages. Included is information on design principles, material selection, board fabrication, assembly technology, testing strategy, and reliability expectations based on end-use environments.