BS EN 60191-6:2009

1 Scope
2 Normative references
3 Terms and definitions
4 Design rules
5 Dimensions to be specified
6 Notes
Annex A (informative) - Illustration of the rules
Annex B (informative) - Optional table format
Bibliography
Annex ZA (normative) - Normative references to international
         publications with their corresponding European
         publications

Provides general rules for the preparation of outline drawings of surface-mounted semiconductor devices.

IEC 60191-6:2009 gives general rules for the preparation of outline drawings of surface-mounted semiconductor devices. It supplements IEC 60191-1 and IEC 60191-3. It covers all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8, as well as integrated circuits classified as form E in Clause 3 of IEC 60191-4. This third edition of IEC 60191-6 cancels and replaces the second edition, published in 2004 and constitutes a technical revision. This edition includes the following significant changes with respect to the previous edition:
a) scope is modified to cover all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8;
b) editorial modifications on several pages; and
c) technical revision to ball grid array package (BGA) especially its geometrical drawing format. (two types of BGA would unify as one type as a result of revising drawing format.