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  • EN 60191-6-21 : 2010

    Current The latest, up-to-date edition.

    MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-21: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGES - MEASURING METHODS FOR PACKAGE DIMENSIONS OF SMALL OUTLINE PACKAGES (SOP)

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    Language(s): 

    Published date:  15-10-2010

    Publisher:  European Committee for Standards - Electrical

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    Table of Contents - (Show below) - (Hide below)

    Foreword
    1 Scope
    2 Normative references
    3 Terms and definitions
    4 Measuring methods
    Annex ZA (normative) - Normative references to international
             publications with their corresponding European
             publications

    Abstract - (Show below) - (Hide below)

    Defines methods to measure package dimensions of small outline packages (SOP), package outline form E in accordance to IEC 60191-4.

    General Product Information - (Show below) - (Hide below)

    Committee SR 47D
    Document Type Standard
    Publisher European Committee for Standards - Electrical
    Status Current

    Standards Referenced By This Book - (Show below) - (Hide below)

    EN IEC 60191-1:2018 Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices
    I.S. EN IEC 60191-1:2018 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 1: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF DISCRETE DEVICES

    Standards Referencing This Book - (Show below) - (Hide below)

    IEC 60191-6:2009 Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
    IEC 60191-4:2013 Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages
    EN 60191-6:2009 Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
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