Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)

Available format(s)

Hardcopy , PDF , PDF 3 Users , PDF 5 Users , PDF 9 Users

Language(s)

English, English - French

Published date

27-01-2011

Publisher

International Electrotechnical Committee

€197.53

Excluding VAT

Product format

I agree to the DRM document license rules apply against the PDF selection made.

Please confirm that you agree to the document license rules for this document.

I agree to the document license rules .

Please confirm that you agree to the document license rules for this document.

FOREWORD
INTRODUCTION
1 Scope
2 Normative references
3 Definitions
4 Terminal position numbering
5 Drawings
6 Dimensions
7 Dimension table

IEC 60191-6-17:2011 provides outline drawings and dimensions for stacked packages and individual stackable packages in the form of FBGA or FLGA.

Committee	TC 47/SC 47D
DevelopmentNote	Stability Date: 2017. (10/2012)
DocumentType	Standard
Pages	58
PublisherName	International Electrotechnical Committee
Status	Current

IEC 60191-6:2009	Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
IEC 60191-6-5:2001	Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)

Access your standards online with a subscription

Features

IEC 60191-6-17:2011